1. Field of the Invention
The invention relates to a method of fabricating an dynamic random access memory (DRAM), and more particularly to a method of fabricating a capacitor with a higher capacitance in a DRAM, by increasing surface area of an electrode.
2. Description of the Related Art
As the function of a microprocessor becomes more and more powerful, the program and calculation of a software becomes more and more complicated, and thus, the required capacitance of a memory is larger and larger. FIG. 1 shows a circuit diagram of a conventional DRAM. A memory cell comprises a transfer transistor 10 and a storing capacitor 11. The source region of the transfer transistor 10 is coupled with a corresponding bit line 12, whereas the gate is coupled with a corresponding word line 13. The drain region of the transfer transistor 10 electrically connects with the storing electrode 14, that is, the bottom electrode of the capacitor 11. The plate electrode 15, that is, the top electrode or the cell electrode, connects with a constant voltage source. A dielectric layer 16 is formed between the storing electrode and the plate electrode.
The capacitor is the heart for storing input signal in a DRAM. For a large amount of charges to be stored in a capacitor, it is more frequent that an soft error is caused by noise, such as an .alpha. particle, during data access, and therefore, the refresh frequency is reduced. Several ways are available to increase the storing capacitance of a capacitor. (1) Using a dielectric layer with a higher dielectric constant, the storing charge per unit area is increased. (2) To decrease the thickness of the dielectric layer, a higher capacitance can be obtained. However, the quality of the dielectric layer restricts the thickness of the dielectric layer to a certain value. (3) By increasing the surface area of a capacitor, the amount of charges stored in a capacitor is increased. However, with increasing the surface area of a capacitor, the integration of a device is decreased.
For a conventional DRAM with a smaller amount of storing charges, a two dimensional planar type capacitor is adapted in a integrated circuit. The planar type capacitor occupies a sizeable surface area on the substrate, and therefore, not suitable for the use in a high integrated circuit. To achieve a high integration, a three dimensional structure of a capacitor, such as a stacked type or a trench type capacitor is adapted. However, as the integration becomes further higher, a pure three dimensional capacitor can not meet the requirement to be used. A method of increasing capacitance in a small area of a capacitor in a DRAM is developed.
Referring to FIG. 2a to FIG. 2c, a conventional method of fabricating a stack capacitor in a DRAM is shown. Referring to FIG. 2a, on a semiconductor substrate 200, a metal-oxide semiconductor (MOS) comprising a source/drain region 201, a gate 203, a field oxide layer 202, a oxide layer 204, and a poly-via 205 are formed. The poly-via 205 penetrates through the oxide layer 204 to electrically connects the source/drain region 201 of the MOS.
Referring to FIG. 2b, a poly-silicon layer 206 is formed on the oxide layer 206, for example, by using chemical vapour deposition (CVD). The poly-silicon layer 206 is then defined by photo-lithography and etching as shown in the figure.
Referring to FIG. 2c, using photo-lithography and etching, the poly-silicon layer 206 is further defined to formed as a bottom electrode 206a. On the bottom electrode 206a, a dielectric layer 207 and a top electrode are formed sequentially to complete a stack capacitor structure in a DRAM.
Referring to FIG. 3, a stacked type capacitor of a DRAM is shown. A semiconductor substrate 30 comprising a MOS transistor 32 which includes a gate 33, a source/drain region 34 and a spacer 35, a field oxide layer 36, and a conductive layer 37 is provided. An insulation layer 38 is formed and patterned over the substrate 30, so that a contact window is formed to expose the source/drain region 34. A bottom electrode 39, a dielectric layer 310, and a top electrode 311 is formed within and on the contact window in sequence to complete the stacked type capacitor 312. The dielectric layer 310 includes a nitride/oxide layer (ON) or an oxide/nitride/oxide (ONO) layer. The bottom electrode 39 and the top electrode 311 include poly-silicon layer. The bottom electrode 39 includes a ragged structure. After the process of forming metal contact and insulation passivation layers, the formation of a DRAM is completed.
In the conventional method of fabricating a capacitor of a DRAM, by improving the topography of a capacitor, for example, forming a ragged surface, the capacitance is increased. However, the increase of capacitance is not enough to meet the requirement of a further smaller devices. In addition, the fabrication process is complex for the conventional method. For example, in the above method, two steps of photolithography and etching steps are in use. Therefore, the possibility of causing a misalignment and an error during exposure is increased. The reliability of device is lowered, the device is degraded, and the production cost is increased.